Jihwan Kimetal., “A 16-to-40 Gb/s Quarter-Rate NRZ/PAM4 Dual-Model Transmitter in 14 nm CMOS”, 2015 IEEE International Solid-State Circuits Conference (ISSCC), (US), February, 2015 (hereinafter, referred to as Non-Patent Literature 1) discloses a signal multiplexer which multiplexes four input signals and outputs one output signal (multiplexed signal). The signal multiplexer includes four buffer sections connected in parallel. Each buffer section includes a flip-flop and two transfer gates which are sequentially connected in series. Each transfer gate is adjusted so as to be turned ON at a predetermined timing. Thus, input signals input to the buffer sections are sequentially output from the signal multiplexer as one output signal.
According to the signal multiplexer disclosed in Non-Patent Literature 1, it is possible to extend the allowable range of the delay time of a flip-flop and accelerate the data rate compared with the case in which two input signals are multiplexed and one output signal is output.